Monday, 16 February 2009

ETL Mark: 3 x TOSEC

"The ETL Mark VI Transistor Computer was completed at the Electrotechnical Laboratory in March 1966. The project began in 1959, and in order to achieve a machine surpassing the ultra-high speed machines of the time from overseas, it was supported with a budget of ¥100 million (20 times that of the Mark IV), and a variety of new technologies were developed for this machine including: high-speed transistor-based basic circuits, high-speed magnetic core memory, a page address system, a high-speed high-capacity fixed memory unit, a sophisticated lookahead control system, high-speed arithmetic circuits, and an input/output control system employing interrupt technology. The high-speed basic circuits were dynamic circuits employing a 2-phase clock pulse with a combination of transistor current switches and emitter followers. Electromagnetic delay lines were used for the short delays not involving logic. These technologies were used in a slightly changed form in the HITAC 5020 from Hitachi."(

Download from Rapidshare:

ETL Mark 2 - Utilities (TOSEC-v2005-03-01)
ETL Mark 4 - Utilities (TOSEC-v2005-03-01)
ETL Mark 4a - Utilities (TOSEC-v2005-03-01)

Megaupload Mirror:

1 comment:

  1. This comment has been removed by a blog administrator.